An Analytical 2-D Model of Triple Metal Double Gate Graded Channel Junctionless MOSFET with Hetero-dielectric Gate Oxide Stack

TL;DR

This paper presents an analytical 2-D model for a novel triple-metal double-gate junctionless MOSFET with hetero-dielectric stack, demonstrating improved performance, control, and reliability in sub-30 nm regimes.

Contribution

It introduces a new analytical model for a graded-channel triple-metal double-gate JLFET with hetero-dielectric stack, highlighting enhanced device performance and reliability.

Findings

Higher drive current and better SCE/HCE suppression in sub-30 nm regime.

Improved threshold voltage, DIBL, and sub-threshold swing.

Validation with numerical calculations confirms superior performance.

Abstract

In this paper, a two-dimensional analytical model of a laterally graded-channel triple-metal double-gate Junctionless Field Effect Transistor with hetero dielectric gate oxide stack consisting of SiO$_2$ and HfO$_2$ is derived. The model illustrates higher drive current and better performance against hazardous SCEs and HCEs in below 30 nm regime. Parabolic approximation method is used here to construct channel potentials and electric fields by solving 2-D Poisson's equation with applicable boundary conditions. The basic central and surface potentials as well as central and surface electric fields are being illustrated, Threshold voltage, DIBL, sub-threshold swing (SS) and a compact current model have also been deduced. These parameters clearly show the benefits of proposed graded-channel triple-metal double-gate structure with hetero-dielectric gate oxide stack. The device has reliability in low power applications because of its better Ion and Ioff control. Finally, the analytical model is validated with self-consistent numerical calculations to illustrate better performance of among available junctionless devices.