IEEE 802.1AS Clock Synchronization Performance Evaluation of an Integrated Wired-Wireless TSN Architecture

TL;DR

This paper evaluates the clock synchronization performance of a hybrid wired-wireless TSN architecture, demonstrating that FPGA-based implementations can meet TSN synchronization requirements in industrial networks.

Contribution

It introduces two FPGA-based hardware architectures for clock synchronization in hybrid wired-wireless TSN networks, leveraging existing Ethernet TSN and wireless technologies.

Findings

Hardware architectures meet TSN synchronization performance

Experimental validation confirms feasibility

Integration of wired and wireless TSN is achievable

Abstract

Industrial control systems present numerous challenges from the communication systems perspective: clock synchronization, deterministic behavior, low latency, high reliability, flexibility, and scalability. These challenges are mostly solved with standard technologies over Ethernet, e.g., Time-Sensitive Networking (TSN). As a research trend, it is expected that TSN will converge with wireless, leading to the Wireless TSN paradigm. Also, Wireless TSN is expected to be integrated with Ethernet TSN to create large-scale wired-wireless (Hybrid) TSN networks. The first step towards Hybrid TSN is the distribution of the clock reference from the wired to the wireless domain. In this paper, we leverage existing Ethernet TSN and wireless technologies implementations (Wi-Fi and w-SHARP) and we present two hardware architectures specifically engineered to enable the clock synchronization distribution among the network domains. The hardware architectures have been implemented over a System-on-Chip (SoC) Field Programmable Gate Array (FPGA) platform. We demonstrate through several experiments that the implementation is able to fulfill the synchronization performance required by TSN.