Design Space Exploration of SABER in 65nm ASIC

TL;DR

This paper explores the design space of SABER cryptographic architecture on a 65nm ASIC, optimizing for high clock frequency and low area, resulting in a tapeout-ready layout suitable for high-speed applications.

Contribution

It introduces a comprehensive design space exploration for SABER on 65nm ASIC, including optimizations like memory compilation, pipelining, and logic sharing, achieving 1GHz operation.

Findings

Achieved 1GHz clock frequency in optimized architecture

Developed a tapeout-ready layout for high-speed SABER ASIC

Estimated power consumption around 184-187mW

Abstract

This paper presents a design space exploration for SABER, one of the finalists in NIST's quantum-resistant public-key cryptographic standardization effort. Our design space exploration targets a 65nm ASIC platform and has resulted in the evaluation of 6 different architectures. Our exploration is initiated by setting a baseline architecture which is ported from FPGA. In order to improve the clock frequency (the primary goal in our exploration), we have employed several optimizations: (i) use of compiled memories in a 'smart synthesis' fashion, (ii) pipelining, and (iii) logic sharing between SABER building blocks. The most optimized architecture utilizes four register files, achieves a remarkable clock frequency of 1GHz while only requiring an area of 0.314mm2. Moreover, physical synthesis is carried out for this architecture and a tapeout-ready layout is presented. The estimated dynamic power consumption of the high-frequency architecture is approximately 184mW for key generation and 187mW for encapsulation or decapsulation operations. These results strongly suggest that our optimized accelerator architecture is well suited for high-speed cryptographic applications.