Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators

TL;DR

Union is a comprehensive HW-SW co-design ecosystem built on MLIR that enables systematic exploration and evaluation of tensor operation mappings on spatial accelerators, facilitating efficient design and optimization.

Contribution

This work introduces Union, a novel MLIR-based framework that unifies hardware-software co-design for spatial accelerators with extensible cost models and mapping abstractions.

Findings

Effective exploration of tensor operation mappings demonstrated.

Case studies show improved understanding of hardware constraints.

Framework supports diverse accelerator architectures and algorithms.

Abstract

To meet the extreme compute demands for deep learning across commercial and scientific applications, dataflow accelerators are becoming increasingly popular. While these "domain-specific" accelerators are not fully programmable like CPUs and GPUs, they retain varying levels of flexibility with respect to data orchestration, i.e., dataflow and tiling optimizations to enhance efficiency. There are several challenges when designing new algorithms and mapping approaches to execute the algorithms for a target problem on new hardware. Previous works have addressed these challenges individually. To address this challenge as a whole, in this work, we present a HW-SW co-design ecosystem for spatial accelerators called Union within the popular MLIR compiler infrastructure. Our framework allows exploring different algorithms and their mappings on several accelerator cost models. Union also includes a plug-and-play library of accelerator cost models and mappers which can easily be extended. The algorithms and accelerator cost models are connected via a novel mapping abstraction that captures the map space of spatial accelerators which can be systematically pruned based on constraints from the hardware, workload, and mapper. We demonstrate the value of Union for the community with several case studies which examine offloading different tensor operations(CONV/GEMM/Tensor Contraction) on diverse accelerator architectures using different mapping schemes.