In-filter Computing For Designing Ultra-light Acoustic Pattern Recognizers

TL;DR

This paper introduces an in-filter computing framework that integrates feature extraction and classification into a single, lightweight SVM architecture optimized for FPGA-based IoT devices, enabling efficient acoustic pattern recognition.

Contribution

The paper proposes a novel in-filter computing approach that combines convolution and nonlinear filtering directly into SVM kernels for ultra-light acoustic classifiers.

Findings

Achieves robust sound classification on benchmark tasks.

Uses only ~1.5k LUTs and ~2.8k FFs on FPGA.

Significantly reduces computational and memory footprint.

Abstract

We present a novel in-filter computing framework that can be used for designing ultra-light acoustic classifiers for use in smart internet-of-things (IoTs). Unlike a conventional acoustic pattern recognizer, where the feature extraction and classification are designed independently, the proposed architecture integrates the convolution and nonlinear filtering operations directly into the kernels of a Support Vector Machine (SVM). The result of this integration is a template-based SVM whose memory and computational footprint (training and inference) is light enough to be implemented on an FPGA-based IoT platform. While the proposed in-filter computing framework is general enough, in this paper, we demonstrate this concept using a Cascade of Asymmetric Resonator with Inner Hair Cells (CAR-IHC) based acoustic feature extraction algorithm. The complete system has been optimized using time-multiplexing and parallel-pipeline techniques for a Xilinx Spartan 7 series Field Programmable Gate Array (FPGA). We show that the system can achieve robust classification performance on benchmark sound recognition tasks using only ~ 1.5k Look-Up Tables (LUTs) and ~ 2.8k Flip-Flops (FFs), a significant improvement over other approaches.