n-bit Data Parallel Spin Wave Logic Gate

TL;DR

This paper introduces a novel n-bit data parallel spin wave logic gate that enables simultaneous processing of multiple data bits in the same waveguide, significantly reducing area without increasing delay or energy use.

Contribution

The paper presents a new computation paradigm for parallel data processing using spin wave properties, demonstrated by an 8-bit 3-input Majority gate implementation.

Findings

8-bit parallel gate requires 4.16x less area than scalar implementation

Parallel processing preserves delay and energy efficiency

Validated through OOMMF simulations

Abstract

Due to their very nature, Spin Waves (SWs) created in the same waveguide, but with different frequencies, can coexist while selectively interacting with their own species only. The absence of inter-frequency interferences isolates input data sets encoded in SWs with different frequencies and creates the premises for simultaneous data parallel SW based processing without hardware replication or delay overhead. In this paper we leverage this SW property by introducing a novel computation paradigm, which allows for the parallel processing of n-bit input data vectors on the same basic SW based logic gate. Subsequently, to demonstrate the proposed concept, we present 8-bit parallel 3-input Majority gate implementation and validate it by means of Object Oriented MicroMagnetic Framework (OOMMF) simulations. To evaluate the potential benefit of our proposal we compare the 8-bit data parallel gate with equivalent scalar SW gate based implementation. Our evaluation indicates that 8-bit data 3-input Majority gate implementation requires 4.16x less area than the scalar SW gate based equivalent counterpart while preserving the same delay and energy consumption figures.