Timing constraints imposed by classical digital control systems on photonic implementations of measurement-based quantum computing

TL;DR

This paper examines the classical digital control system's timing constraints in photonic measurement-based quantum computing, emphasizing the need for co-design to meet system speed and accuracy requirements.

Contribution

It provides a detailed analysis of the timing constraints imposed by digital control hardware on photonic MBQC, highlighting the importance of co-design for system scalability.

Findings

Static timing analysis sets an upper bound on adaptive measurement speed.

Timing constraints significantly influence the photonic clock rate.

Co-design of classical and quantum systems is crucial for scalable photonic quantum computing.

Abstract

Most of the architectural research on photonic implementations of measurement-based quantum computing (MBQC) has focused on the quantum resources involved in the problem with the implicit assumption that these will provide the main constraints on system scaling. However, the `flying-qubit' architecture of photonic MBQC requires specific timing constraints that need to be met by the classical control system. This classical control includes, for example: the amplification of the signals from single-photon detectors to voltage levels compatible with digital systems; the implementation of a control system which converts measurement outcomes into basis settings for measuring subsequent cluster qubits, in accordance with the quantum algorithm being implemented; and the digital-to-analog converter (DAC) and amplifier systems required to set these measurement bases using a fast phase modulator. In this paper, we analyze the digital system needed to implement arbitrary one-qubit rotations and controlled-NOT (CNOT) gates in discrete-variable photonic MBQC, in the presence of an ideal cluster state generator, with the main aim of understanding the timing constraints imposed by the digital logic on the analog system and quantum hardware. We use static timing analysis of a Xilinx FPGA (7 series) to provide a practical upper bound on the speed at which the adaptive measurement processing can be performed, in turn constraining the photonic clock rate of the system. Our work points to the importance of co-designing the classical control system in tandem with the quantum system in order to meet the challenging specifications of a photonic quantum computer.