STL2vec: Signal Temporal Logic Embeddings for Control Synthesis With Recurrent Neural Networks

TL;DR

This paper introduces STL2vec, a novel embedding for STL specifications, enabling the synthesis of RNN controllers that can handle multiple specifications efficiently, demonstrated through path planning examples.

Contribution

The paper proposes STL2vec, a new vector representation of STL specifications, improving RNN controller synthesis for multiple specifications.

Findings

STL2vec effectively captures similarities among STL specifications.

The method enhances RNN controller performance and efficiency.

Validated through path planning case studies.

Abstract

In this paper, a method for learning a recurrent neural network (RNN) controller that maximizes the robustness of signal temporal logic (STL) specifications is presented. In contrast to previous methods, we consider synthesizing the RNN controller for which the user is able to select an STL specification arbitrarily from multiple STL specifications. To obtain such a controller, we propose a novel notion called STL2vec, which represents a vector representation of the STL specifications and exhibits their similarities. The construction of the STL2vec is useful since it allows us to enhance the efficiency and performance of the RNN controller. We validate our proposed method through the examples of the path planning problem.