High-Resolution Waveform Capture Device on a Cyclone-V FPGA

TL;DR

This paper presents a high-resolution waveform capture device implemented on an FPGA that achieves picosecond timing accuracy using a novel calibration method, enabling precise digital signal measurements with open-source tools.

Contribution

The paper introduces a flexible FPGA-based measurement system with a novel dynamic phase-shifting calibration, achieving sub-5 ps resolution and providing open-source code for replication.

Findings

Measurement resolution of ~4.9 ps for high and low pulses.

Single-shot timing error around 29 ps.

Reproduced oscilloscope measurements of FPGA ring-oscillators.

Abstract

We introduce the waveform capture device (WCD), a flexible measurement system capable of recording complex digital signals on trillionth-of-a-second (ps) time scales. The WCD is implemented via modular code on an off-the-shelf field-programmable gate-array (FPGA, Intel/Altera Cyclone V), and incorporates both time-to-digital converter (TDC) and digital storage oscilloscope (DSO) functionality. The device captures a waveform by taking snapshots of a signal as it propagates down an ultra-fast transmission line known as a carry chain (CC). It is calibrated via a novel dynamic phase-shifting (DPS) method that requires substantially less data and resources than the state-of-the-art. Using DPS, we find the measurement resolution - or mean propagation delay from one CC element to the next - to be 4.91 +/- 0.04 ps (4.54 +/- 0.02 ps) for a pulse of logic high (low). Similarly, we find the single-shot precision - or mean error on the timing of the waveform - to be 29.52 ps (27.14 ps) for pulses of logic high (low). We verify these findings by reproducing commercial oscilloscope measurements of asynchronous ring-oscillators on FPGAs, finding the mean pulse width to be 0.240 +/- 0.002 ns per inverter gate. Finally, we present a careful analysis of design constraints, introduce a novel error correction algorithm, and sketch a simple extension to the analog domain. We also provide the Verilog code instantiating the our design on an FPGA in an Appendix, and make our methods available as an open-source Python library at https://github.com/Noeloikeau/fpyga.