Compiler-Driven FPGA Virtualization with SYNERGY

TL;DR

This paper introduces Synergy, a compiler and runtime approach for FPGA virtualization that enables efficient workload management and migration with minimal performance overhead, suitable for cloud data centers.

Contribution

It presents a novel compiler transformation for Verilog that allows FPGA programs to support virtualization primitives like suspend, resume, and migration.

Findings

Workloads run within 3-4x of native performance.

Supports core virtualization primitives efficiently.

Requires no modification to existing FPGA workloads.

Abstract

FPGAs are increasingly common in modern applications, and cloud providers now support on-demand FPGA acceleration in data centers. Applications in data centers run on virtual infrastructure, where consolidation, multi-tenancy, and workload migration enable economies of scale that are fundamental to the provider's business. However, a general strategy for virtualizing FPGAs has yet to emerge. While manufacturers struggle with hardware-based approaches, we propose a compiler/runtime-based solution called Synergy. We show a compiler transformation for Verilog programs that produces code able to yield control to software at sub-clock-tick granularity according to the semantics of the original program. Synergy uses this property to efficiently support core virtualization primitives: suspend and resume, program migration, and spatial/temporal multiplexing, on hardware which is available today. We use Synergy to virtualize FPGA workloads across a cluster of Altera SoCs and Xilinx FPGAs on Amazon F1. The workloads require no modification, run within 3-4x of unvirtualized performance, and incur a modest increase in FPGA fabric utilization.