A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS
Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri,, Simone Benatti, Luca Benini, Davide Rossi

TL;DR
This paper introduces a fully integrated, energy-efficient chip-to-chip transceiver in 65-nm CMOS for IoT end-nodes, achieving high data rates with low power consumption suitable for real-world applications.
Contribution
It presents a novel low-swing transceiver integrated within an IoT system-on-chip, enabling high-speed, energy-efficient communication at milliwatt power levels.
Findings
Achieves 8.46x higher energy efficiency than SPI interface.
Delivers 15.9x higher performance than traditional microcontroller interfaces.
Successfully integrated and tested within a CMOS 65nm IoT system-on-chip.
Abstract
The increasing complexity of Internet-of-Things (IoT) applications and near-sensor processing algorithms is pushing the computational power of low-power, battery-operated end-node systems. This trend also reveals growing demands for high-speed and energy-efficient inter-chip communications to manage the increasing amount of data coming from off-chip sensors and memories. While traditional micro-controller interfaces such as SPIs cannot cope with tight energy and large bandwidth requirements, low-voltage swing transceivers can tackle this challenge thanks to their capability to achieve several Gbps of the communication speed at milliwatt power levels. However, recent research on high-speed serial links focused on high-performance systems, with a power consumption significantly larger than the one of low-power IoT end-nodes, or on stand-alone designs not integrated at a system level. This…
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