In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

TL;DR

This paper introduces an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer readout chip, significantly reducing calibration time and improving usability for high-luminosity collider upgrades.

Contribution

It presents a novel in-pixel calibration scheme with FPGA implementation, TMR redundancy, and verified performance, enhancing calibration efficiency and robustness.

Findings

Calibration process lasts 35 ms at 40 MHz clock

Power consumption is 300 uW (dynamic) and 10.4 uW (static)

Verified with FPGA and SEE simulation

Abstract

We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 uW and 10.4 uW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16x16 pixel matrix.