A Novel Compaction Approach for SBST Test Programs

TL;DR

This paper presents a new method for compressing self-test programs for processor-based devices, significantly reducing size and testing time while maintaining fault coverage, which is crucial for safety-critical applications.

Contribution

It introduces a logic simulation-based compaction technique that analyzes instruction interactions to minimize fault simulations, a novel approach in STL test program compression.

Findings

Test program length reduced by up to 93.9%

Test duration reduced by up to 95%

Minimal impact on fault coverage

Abstract

In-field test of processor-based devices is a must when considering safety-critical systems (e.g., in robotics, aerospace, and automotive applications). During in-field testing, different solutions can be adopted, depending on the specific constraints of each scenario. In the last years, Self-Test Libraries (STLs) developed by IP or semiconductor companies became widely adopted. Given the strict constraints of in-field test, the size and time duration of a STL is a crucial parameter. This work introduces a novel approach to compress functional test programs belonging to an STL. The proposed approach is based on analyzing (via logic simulation) the interaction between the micro-architectural operation performed by each instruction and its capacity to propagate fault effects on any observable output, reducing the required fault simulations to only one. The proposed compaction strategy was validated by resorting to a RISC-V processor and several test programs stemming from diverse generation strategies. Results showed that the proposed compaction approach can reduce the length of test programs by up to 93.9% and their duration by up to 95%, with minimal effect on fault coverage.