Self-timed Reinforcement Learning using Tsetlin Machine

TL;DR

This paper introduces a low-energy, asynchronous hardware design for the Tsetlin machine's learning process, enhancing AI applications in energy-constrained environments like healthcare and IoT.

Contribution

It presents a novel asynchronous hardware implementation of the Tsetlin machine's learning datapath, including detailed analysis and design techniques for improved energy efficiency and latency.

Findings

Asynchronous design reduces energy consumption.

The hardware achieves low latency suitable for IoT devices.

Addressed challenges of static timing analysis in asynchronous circuits.

Abstract

We present a hardware design for the learning datapath of the Tsetlin machine algorithm, along with a latency analysis of the inference datapath. In order to generate a low energy hardware which is suitable for pervasive artificial intelligence applications, we use a mixture of asynchronous design techniques - including Petri nets, signal transition graphs, dual-rail and bundled-data. The work builds on previous design of the inference hardware, and includes an in-depth breakdown of the automaton feedback, probability generation and Tsetlin automata. Results illustrate the advantages of asynchronous design in applications such as personalized healthcare and battery-powered internet of things devices, where energy is limited and latency is an important figure of merit. Challenges of static timing analysis in asynchronous circuits are also addressed.