Probabilistic Verification for Reliability of a Two-by-Two Network-on-Chip System
Riley Roberts, Benjamin Lewis, Arnd Hartmanns, Prabal Basu,, Sanghamitra Roy, Koushik Chakraborty, and Zhen Zhang

TL;DR
This paper introduces a probabilistic model checking approach to analyze power supply noise in a 2x2 mesh network-on-chip, revealing optimal traffic patterns to enhance reliability by minimizing voltage droop-induced errors.
Contribution
It presents a novel probabilistic abstraction method and applies formal verification to assess PSN in NoC systems, addressing state explosion issues.
Findings
Optimal flit pattern with zero PSN probability identified
Spreading flits reduces voltage droop and errors
Probabilistic model checking effectively analyzes NoC reliability
Abstract
Modern network-on-chip (NoC) systems face reliability issues due to process and environmental variations. The power supply noise (PSN) in the power delivery network of a NoC plays a key role in determining reliability. PSN leads to voltage droop, which can cause timing errors in the NoC. This paper makes a novel contribution towards formally analyzing PSN in NoC systems. We present a probabilistic model checking approach to observe the PSN in a generic 2x2 mesh NoC with a uniform random traffic load. Key features of PSN are measured at the behavioral level. To tackle state explosion, we apply incremental abstraction techniques, including a novel probabilistic choice abstraction, based on observations of NoC behavior. The Modest Toolset is used for probabilistic modeling and verification. Results are obtained for several flit injection patterns to reveal their impacts on PSN. Our…
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Taxonomy
TopicsVLSI and Analog Circuit Testing · Embedded Systems Design Techniques · Formal Methods in Verification
