A Design Flow for Mapping Spiking Neural Networks to Many-Core Neuromorphic Hardware
Shihao Song, M. Lakshmi Varshika, Anup Das, and Nagarajan Kandasamy

TL;DR
This paper presents a predictable design flow using Synchronous Data Flow Graphs for mapping spiking neural networks onto many-core neuromorphic hardware, optimizing for throughput and buffer size.
Contribution
It introduces an SDFG-based design flow with iterative partitioning and evolutionary optimization to improve mapping efficiency and tradeoffs in neuromorphic hardware.
Findings
Achieves 63% higher maximum throughput.
Reduces buffer size requirement by 10%.
Effective for large-scale CNN models.
Abstract
The design of many-core neuromorphic hardware is getting more and more complex as these systems are expected to execute large machine learning models. To deal with the design complexity, a predictable design flow is needed to guarantee real-time performance such as latency and throughput without significantly increasing the buffer requirement of computing cores. Synchronous Data Flow Graphs (SDFGs) are used for predictable mapping of streaming applications to multiprocessor systems. We propose an SDFG-based design flow for mapping spiking neural networks (SNNs) to many-core neuromorphic hardware with the objective of exploring the tradeoff between throughput and buffer size. The proposed design flow integrates an iterative partitioning approach, based on Kernighan-Lin graph partitioning heuristic, creating SNN clusters such that each cluster can be mapped to a core of the hardware. The…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Neural dynamics and brain function
