Terabit-per-Second Multicore Polar Code Successive Cancellation Decoders

TL;DR

This paper introduces a high-throughput, energy-efficient multicore polar code decoder architecture capable of achieving 1 Tb/s throughput, optimized for 28nm ASIC technology, using multiple parallel SC decoders with adaptive quantization.

Contribution

It presents a novel multicore SC decoder architecture with optimized pipeline depth and adaptive quantization, enabling Tb/s throughput and low power consumption.

Findings

Achieves 1 Tb/s throughput with 4-core decoder

Operates at 28nm technology with 1.55 pJ/bit energy efficiency

Uses adaptive LLR quantization for complexity reduction

Abstract

This work presents a high throughput and energy efficient multicore (MC) successive cancellation (SC) decoder architecture for polar codes. SC is a low-complexity decoding algorithm with a set of sequential operations. The sequential processing nature of SC limits parallelism but promotes not only pipelining but also multiple copies of SC decoder with an optimized pipeline depth to achieve Tb/s throughput. The MCSC decoder architecture consists of multiple SC decoders with lower frequency and pipeline depth to process multiple codewords in parallel to achieve lower power consumption. The pipeline depth of MCSC is optimized separately for each multicore configuration using register reduction/balancing (R-RB) method. This enables an efficient implementation for the 1-core, 2-core 4-core and 8-core candidate MCSC decoders. To reduce the complexity of the implementation, an adaptive log-likelihood ratio (LLR) quantization scheme is used for internal LLRs within the range of 1-5 bits. The post-placement-routing results at 28nm High-k Metal Gate (HKMG) ASIC technology show that 4-core MCSC decoder achieves 1 Tb/s throughput on 3.92 mm$^2$ area with 1.55 pJ/bit energy efficiency.