Synthesis of Predictable Global NoC by Abutment in Synchoros VLSI Design

TL;DR

This paper introduces a novel VLSI design approach called Synchoros, using SiLago blocks to automatically synthesize valid, cost-efficient global NoCs with accurate timing analysis in linear time, facilitating chip-level design exploration.

Contribution

It presents a new design style and methodology for synthesizing global NoCs using SiLago blocks, enabling automatic, valid, and cost-aware design with linear-time timing analysis.

Findings

Global NoCs can be synthesized automatically with known cost metrics.

Abstract timing models match commercial static timing analysis results.

Design space exploration is facilitated by linear-time synthesis and analysis.

Abstract

Synchoros VLSI design style has been proposed as an alternative to the standard cell best design style; the word synchoros is derived from the Greek word choros for space. Synchoricity discretises space with a virtual grid, the way synchronicity discretises time with clock ticks. SiLago (Silicon Lego) blocks are atomic synchoros building blocks like Lego bricks. SiLago blocks absorb all metal layer details, i.e., all wires, to enable composition by abutment of valid; valid in the sense of being technology design rules compliant, timing clean and OCV ruggedized. Effectively, composition by abutment eliminates logic and physical synthesis for the end user. Like Lego system, synchoricity does need a finite number of SiLago block types to cater to different types of designs. Global NoCs are important system level design components. In this paper, we show, how with a small library of SiLago blocks for global NoCs, it is possible to automatically synthesize arbitrary global NoCs of different types, dimensions, and topology. The synthesized global NoCs are not only valid VLSI designs, their cost metrics (area, latency, and energy) are known with post-layout accuracy in linear time. We argue that this is essential to be able to do chip-level design space exploration. We show how the abstract timing model of such global NoC SiLago blocks can be built and used to analyse the timing of global NoC links with post layout accuracy and in linear time. We validate this claim by subjecting the same VLSI designs of global NoC to commercial EDA's static timing analysis and show that the abstract timing analysis enabled by synchoros VLSI design gives same results as the commercial EDA tools.