Efficient On-Chip Communication for Parallel Graph-Analytics on Spatial Architectures

TL;DR

This paper introduces a power-law aware graph partitioning and data mapping scheme for spatial architectures, significantly reducing data movement bottlenecks and improving execution speed and energy efficiency in large-scale graph processing.

Contribution

It proposes a novel data partitioning and mapping method tailored for spatial architectures to mitigate data movement bottlenecks in parallel graph processing.

Findings

Execution speed improved by 2-5x

Energy efficiency increased by 2.7-4x

Reduced data movement latency in graph algorithms

Abstract

Large-scale graph processing has drawn great attention in recent years. Most of the modern-day datacenter workloads can be represented in the form of Graph Processing such as MapReduce etc. Consequently, a lot of designs for Domain-Specific Accelerators have been proposed for Graph Processing. Spatial Architectures have been promising in the execution of Graph Processing, where the graph is partitioned into several nodes and each node works in parallel. We conduct experiments to analyze the on-chip movement of data in graph processing on a Spatial Architecture. Based on the observations, we identify a data movement bottleneck, in the execution of such highly parallel processing accelerators. To mitigate the bottleneck we propose a novel power-law aware Graph Partitioning and Data Mapping scheme to reduce the communication latency by minimizing the hop counts on a scalable network-on-chip. The experimental results on popular graph algorithms show that our implementation makes the execution 2-5x faster and 2.7-4x energy-efficient by reducing the data movement time in comparison to a baseline implementation.