CMOS back-end-of-line compatible ferroelectric tunnel junction devices

TL;DR

This paper demonstrates CMOS-compatible ferroelectric tunnel junctions using hafnium zirconium oxide, enabling low-power memory and computing applications with a process compatible with existing semiconductor manufacturing.

Contribution

It presents a CMOS back-end-of-line compatible ferroelectric tunnel junction device architecture based on Hf0.5Zr0.5O2 with low-temperature annealing.

Findings

Device performance comparable to higher temperature processes.

CMOS integration of ferroelectric devices demonstrated.

Low-temperature annealing preserves device functionality.

Abstract

Ferroelectric tunnel junction devices based on ferroelectric thin films of solid solutions of hafnium dioxide can enable CMOS integration of ultra-low power ferroelectric devices with potential for memory and emerging computing schemes such as in-memory computing and neuromorphic applications. In this work, we present ferroelectric tunnel junctions based on Hf$_{0.5}$Zr$_{0.5}$O$_{2}$ with materials and processes compatible with CMOS back-end-of-line integration. We show a device architecture based on W-Hf$_{0.5}$Zr$_{0.5}$O$_{2}$-Al$_{2}$O$_{3}$-TiN stacks featuring low temperature annealing at 400{\deg}C with performance comparable to those obtained with higher temperature annealing conditions.