Simulations of hybrid charge-sensing single-electron-transistors and CMOS circuits

TL;DR

This paper models and simulates a hybrid system combining single-electron transistors and CMOS circuits, aiming to improve charge sensing and integration for quantum computing and electronic applications.

Contribution

It introduces a simulation framework for paired SETs with CMOS circuits, enhancing signal amplification and integration feasibility.

Findings

Simulated two-stage amplification of SETs and CMOS devices.

Demonstrated direct signal transfer from SETs to CMOS circuits.

Showed potential for improved charge sensing in quantum computing.

Abstract

Single-electron transistors (SETs) have been extensively used as charge sensors in many areas such as quantum computations. In general, the signals of SETs are smaller than those of complementary metal-oxide semiconductor (CMOS) devices, and many amplifying circuits are required to enlarge these signals. Instead of amplifying a single small output, we theoretically consider the amplification of pairs of SETs, such that one of the SETs is used as a reference. We simulate the two-stage amplification process of SETs and CMOS devices using a conventional SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulator. Implementing the pairs of SETs into CMOS circuits makes the integration of SETs more feasible because of direct signal transfer from the SET to the CMOS circuits.