Design of Novel 3T Ternary DRAM with Single Word-Line using CNTFET

TL;DR

This paper introduces a novel ternary 3T-DRAM cell utilizing a single word-line and CNTFET technology, aiming to improve energy efficiency and circuit simplicity in ternary logic systems.

Contribution

It proposes a new 3T-DRAM design with integrated sense circuitry using CNTFETs, analyzed under process variations for improved read/write performance.

Findings

Reduced write delay and sensing time

Lower power consumption

Robust operation under process variations

Abstract

Ternary logic system is the most promising and pursued alternate to the prevailing binary logic systems due to the energy efficiency of circuits following reduced circuit complexity and chip area. In this paper, we have proposed a ternary 3-Transistor Dynamic Random-Access Memory (3T-DRAM) cell using a single word-line for both read and write operation. For simulation of the circuit, we have used Carbon-Nano-Tube Field Effect Transistor (CNTFET). Here, we have analyzed the operation of the circuit considering different process variations and showed the results for write delay, read sensing time, and consumed current. Along with the basic DRAM design, we have proposed a ternary sense circuitry for the proper read operation of the proposed DRAM. The simulation and analysis are executed using the H-SPICE tool with Stanford University CNTFET model.