SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks
Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali, Chakrabarti, Jae-sun Seo, Umit Y. Ogras, Yu Cao

TL;DR
SIAM is a comprehensive benchmarking simulator for chiplet-based in-memory computing architectures, enabling scalable, flexible evaluation of deep neural network acceleration with significant energy-efficiency improvements over GPUs.
Contribution
This work introduces SIAM, a novel end-to-end simulation tool for evaluating chiplet-based IMC architectures, addressing scalability, flexibility, and performance analysis for deep learning acceleration.
Findings
SIAM accurately models chiplet-based IMC systems with integrated device, circuit, and network components.
Benchmarking shows significant energy-efficiency gains over GPUs for ResNet-50 on ImageNet.
SIAM enables efficient design space exploration for large-scale deep learning accelerators.
Abstract
In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic challenges on area, yield, and on-chip interconnection cost due to the ever-increasing model sizes. 2.5D integration or chiplet-based architectures interconnect multiple small chips (i.e., chiplets) to form a large computing system, presenting a feasible solution beyond a monolithic IMC architecture to accelerate large deep learning models. This paper presents a new benchmarking simulator, SIAM, to evaluate the performance of chiplet-based IMC architectures and explore the potential of such a paradigm shift in IMC architecture design. SIAM integrates device, circuit, architecture, network-on-chip (NoC), network-on-package (NoP), and DRAM access models to realize an end-to-end system. SIAM is scalable in its support of a wide range of deep neural networks (DNNs), customizable to various network structures and…
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