Non-Hysteretic Condition in Negative Capacitance Junctionless FETs

TL;DR

This paper presents an analytical framework for designing negative capacitance junctionless FETs that ensures hysteresis-free operation across various temperatures, validated by numerical simulations.

Contribution

It introduces a charge-based model to predict stability, hysteresis voltage, and ferroelectric layer thickness for NCDG JLFETs, advancing design guidelines.

Findings

Analytical expressions for instability and hysteresis voltage.

Design parameters for hysteresis-free operation.

Validation through numerical TCAD simulations.

Abstract

This paper analyzes the design space stability of negative capacitance double gate junctionless FETs (NCDG JLFET). Using analytical expressions derived from a charge-based model, we predict instability condition, hysteresis voltage, and critical thickness of the ferroelectric layers giving rise to the negative capacitance behavior. The impact of the technological parameters is investigated in order to ensure hysteresis-free operation. Finally, the stability of NCDG JLFET is predicted over a wide range of temperatures from 77K to 400K. This approach has been assessed with numerical TCAD simulations.