Optimisation of an FPGA Credit Default Swap engine by embracing dataflow techniques

TL;DR

This paper enhances an FPGA-based Credit Default Swap engine by applying dataflow techniques, achieving significant speedup and power efficiency improvements over traditional CPU implementations.

Contribution

It demonstrates a redesign of an existing FPGA engine using dataflow approaches, resulting in an eightfold speed increase and improved power efficiency compared to CPU solutions.

Findings

Engine is 8x faster on FPGA than original version

FPGA engine outperforms CPU by 1.55x in speed

FPGA consumes 4.7x less power and is 7x more power-efficient

Abstract

Quantitative finance is the use of mathematical models to analyse financial markets and securities. Typically requiring significant amounts of computation, an important question is the role that novel architectures can play in accelerating these models in the future on HPC machines. In this paper we explore the optimisation of an existing, open source, FPGA based Credit Default Swap (CDS) engine using High Level Synthesis (HLS). Developed by Xilinx, and part of their open source Vitis libraries, the implementation of this engine currently favours flexibility and ease of integration over performance. We explore redesigning the engine to fully embrace the dataflow approach, ultimately resulting in an engine which is around eight times faster on an Alveo U280 FPGA than the original Xilinx library version. We then compare five of our engines on the U280 against a 24-core Xeon Platinum Cascade Lake CPU, outperforming the CPU by around 1.55 times, with the FPGA consuming 4.7 times less power and delivering around seven times the power efficiency of the CPU.