A High Performance and Robust FIFO Synchronizer-Interface for Crossing Clock Domains in SFQ Logic

TL;DR

This paper introduces a high-performance, robust FIFO synchronizer and interface for clock domain crossing in SFQ logic, enabling reliable data transfer in ultra-fast, low-power supercomputing circuits.

Contribution

It presents a novel FIFO synchronizer and interface design tailored for SFQ logic, supporting uni- and bi-directional data transfer without frequency degradation.

Findings

Supports complex SFQ logic cores with low BER

Unaffected by noise with current SFQ lithography

Maintains high clock frequency during data transfer

Abstract

Digital single-flux quantum (SFQ) technology promises to meet the demands of ultra low power and high speed computing needed for future exascale supercomputing platforms. However, clocking SFQ logic circuits remains a challenge due to the presence of a large number of on-chip clock sinks, and hence, decomposing large designs into multiple independent clock domains similar to CMOS, have been proposed. However, such clock domains demand efficient synchronizing First-in-first-out (FIFO) buffers and robust interfaces to safely transfer data from one clock domain to another. In this brief, we propose such a FIFO synchronizer and clock-domain crossing interface for both uni and bi-directional data transfer without any significant degradation of the clock frequency. Our proposal scales to complex gate-level pipelined SFQ logic cores while demonstrating extremely low Bit Error Rate (BER) and is unaffected by noise, given current SFQ lithography feature sizes.