Clio: A Hardware-Software Co-Designed Disaggregated Memory System
Zhiyuan Guo, Yizhou Shan, Xuhao Luo, Yutong Huang, Yiying Zhang

TL;DR
Clio is a hardware-software co-designed disaggregated memory system that offers high throughput, low latency, scalability, and energy efficiency by integrating processing power at memory nodes.
Contribution
We introduce Clio, a novel hardware-based disaggregated memory system with integrated processing, co-designed with OS, hardware, and network components for improved performance and management.
Findings
Achieves 100 Gbps throughput per memory node
End-to-end latency of 2.5 microseconds median
Outperforms RDMA and SmartNIC-based systems in scalability and energy efficiency
Abstract
Memory disaggregation has attracted great attention recently because of its benefits in efficient memory utilization and ease of management. So far, memory disaggregation research has all taken one of two approaches: building/emulating memory nodes using regular servers or building them using raw memory devices with no processing power. The former incurs higher monetary cost and faces tail latency and scalability limitations, while the latter introduces performance, security, and management problems. Server-based memory nodes and memory nodes with no processing power are two extreme approaches. We seek a sweet spot in the middle by proposing a hardware-based memory disaggregation solution that has the right amount of processing power at memory nodes. Furthermore, we take a clean-slate approach by starting from the requirements of memory disaggregation and designing a…
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Taxonomy
TopicsCloud Computing and Resource Management · Software-Defined Networks and 5G · Parallel Computing and Optimization Techniques
