Asymmetry-aware Scalable Locking

TL;DR

LibASL is a novel asymmetry-aware scalable lock designed for asymmetric multicore processors, significantly improving throughput while maintaining specified latency requirements.

Contribution

This paper introduces LibASL, the first lock that adapts to core asymmetry, enabling better scalability and latency control on AMP architectures.

Findings

LibASL improves throughput by up to 5x.

LibASL preserves application-specified tail latency.

LibASL is easy to integrate with existing applications.

Abstract

The pursuit of power-efficiency is popularizing asymmetric multicore processors (AMP) such as ARM big.LITTLE, Apple M1 and recent Intel Alder Lake with big and little cores. However, we find that existing scalable locks fail to scale on AMP and cause collapses in either throughput or latency, or both, because their implicit assumption of symmetric cores no longer holds. To address this issue, we propose the first asymmetry-aware scalable lock named LibASL. LibASL provides a new lock ordering guided by applications' latency requirements, which allows big cores to reorder with little cores for higher throughput under the condition of preserving applications' latency requirements. Using LibASL only requires linking the applications with it and, if latency-critical, inserting few lines of code to annotate the coarse-grained latency requirement. We evaluate LibASL in various benchmarks including five popular databases on Apple M1. Evaluation results show that LibASL can improve the throughput by up to 5 times while precisely preserving the tail latency designated by applications.