From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics

TL;DR

This paper presents an automated tool flow that translates a domain-specific language into FPGA accelerators for fluid dynamics simulations, improving resource utilization and performance.

Contribution

It introduces a novel DSL-based flow for FPGA accelerator generation and a decoupled optimization approach for memory and logic resources.

Findings

Doubling the number of parallel kernels

Increasing speedup from 7x to 12x over ARM

Enhanced resource utilization efficiency

Abstract

Many applications are increasingly requiring numerical simulations for solving complex problems. Most of these numerical algorithms are massively parallel and often implemented on parallel high-performance computers. However, classic CPU-based platforms suffers due to the demand for higher resolutions and the exponential growth of data. FPGAs offer a powerful and flexible alternative that can host accelerators to complement such platforms. Developing such application-specific accelerators is still challenging because it is hard to provide efficient code for hardware synthesis. In this paper, we study the challenges of porting a numerical simulation kernel onto FPGA. We propose an automated tool flow from a domain-specific language (DSL) to generate accelerators for computational fluid dynamics on FPGA. Our DSL-based flow simplifies the exploration of parameters and constraints such as on-chip memory usage. We also propose a decoupled optimization of memory and logic resources, which allows us to better use the limited FPGA resources. In our preliminary evaluation, this enabled doubling the number of parallel kernels, increasing the accelerator speedup versus ARM execution from 7 to 12 times.