BEANNA: A Binary-Enabled Architecture for Neural Network Acceleration
Caleb Terrill, Fred Chu

TL;DR
BEANNA is a specialized neural network accelerator that efficiently processes both floating point and binary layers, significantly improving throughput and reducing memory and energy use for mobile and embedded AI applications.
Contribution
This paper introduces BEANNA, a novel hardware architecture with a 16x16 systolic array that seamlessly switches between floating point and binary neural network processing.
Findings
Achieves 52.8 GigaOps/sec in high precision mode
Reaches 820 GigaOps/sec in binary mode
Provides 194% throughput increase with minimal accuracy loss
Abstract
Modern hardware design trends have shifted towards specialized hardware acceleration for computationally intensive tasks like machine learning and computer vision. While these complex workloads can be accelerated by commercial GPUs, domain-specific hardware is far more optimal when needing to meet the stringent memory, throughput, and power constraints of mobile and embedded devices. This paper proposes and evaluates a Binary-Enabled Architecture for Neural Network Acceleration (BEANNA), a neural network hardware accelerator capable of processing both floating point and binary network layers. Through the use of a novel 16x16 systolic array based matrix multiplier with processing elements that compute both floating point and binary multiply-adds, BEANNA seamlessly switches between high precision floating point and binary neural network layers. Running at a clock speed of 100MHz, BEANNA…
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Taxonomy
TopicsCCD and CMOS Imaging Sensors · Parallel Computing and Optimization Techniques · Advanced Memory and Neural Computing
