Hardware-aware Design of Multiplierless Second-Order IIR Filters with Minimum Adders

TL;DR

This paper presents a global optimization approach for designing multiplierless second-order IIR filters with minimal adders, combining coefficient design, quantization, and implementation into a single ILP problem, leading to hardware-efficient filters.

Contribution

It introduces a unified optimization framework for multiplierless filter design that guarantees specifications and stability, improving hardware efficiency over existing methods.

Findings

Achieves 42% reduction in lookup tables compared to state-of-the-art methods.

Attains 21% improvement in delay over traditional three-step design approaches.

Successfully implements filters within FPGA using FloPoCo, demonstrating practical benefits.

Abstract

In this work, we optimally solve the problem of multiplierless design of second-order Infinite Impulse Response filters with minimum number of adders. Given a frequency specification, we design a stable direct form filter with hardware-aware fixed-point coefficients that yielding minimal number of adders when replacing all the multiplications by bit shifts and additions. The coefficient design, quantization and implementation, typically conducted independently, are now gathered into one global optimization problem, modeled through integer linear programming and efficiently solved using generic solvers. We guarantee the frequency-domain specifications and stability, which together with optimal number of adders will significantly simplify design-space exploration for filter designers. The optimal filters are implemented within the FloPoCo IP core generator and synthesized for Field Programmable Gate Arrays. With respect to state-of-the-art three-step filter design methods, our one-step design approach achieves, on average, 42% reduction in the number of lookup tables and 21% improvement in delay.