Synthesizing Brain-Network-Inspired Interconnections for Large-Scale Network-on-Chips

TL;DR

This paper introduces a brain-network-inspired topology for large-scale network-on-chips, achieving lower latency and hop count through novel synthesis, application mapping, and routing methods validated by extensive simulations.

Contribution

It presents a new method to generate brain-inspired topologies with desirable properties and an application mapping approach to optimize power and latency in large-scale NoCs.

Findings

Significantly lower average hop count and latency compared to traditional topologies.

Up to 70% reduction in hop count for graph processing applications.

Up to 75% reduction in latency in power-law, tightly coupled inter-core communication scenarios.

Abstract

Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In this paper, we propose to synthesize brain-network-inspired interconnections for large-scale network-on-chips. Firstly, we propose a method to generate brain-network-inspired topologies with limited scale-free and power-law small-world properties, which have a low total link length and extremely low average hop count approximately proportional to the logarithm of the network size. In addition, given the large-scale applications and the modular topology, we present an application mapping method, including task mapping and deterministic deadlock-free routing, to minimize the power consumption and hop count. Finally, a cycle-accurate simulator BookSim2 is used to validate the architecture performance with different synthetic traffic patterns and large-scale test cases, including real-world communication networks for the graph processing application. Experiments show that, compared with other topologies and methods, the NoC design generated by the proposed method presents significantly lower average hop count and lower average latency. Especially in graph processing applications with a power-law and tightly coupled inter-core communication, the brain-network-inspired NoC has up to 70% lower average hop count and 75% lower average latency than mesh-based NoCs.