Efficient On-Chip Multicast Routing based on Dynamic Partition Merging

TL;DR

This paper introduces a dynamic partition merging multicast routing algorithm for Networks-on-Chips that optimizes path selection, significantly improving latency and power efficiency in CMP applications.

Contribution

It presents a novel dynamic partition merging approach for multicast routing that outperforms static strategies by optimizing routing costs.

Findings

Up to 23% reduction in average packet latency.

Up to 14% decrease in power consumption.

Outperforms existing path-based routing algorithms in simulations.

Abstract

Networks-on-chips (NoCs) have become the mainstream communication infrastructure for chip multiprocessors (CMPs) and many-core systems. The commonly used parallel applications and emerging machine learning-based applications involve a significant amount of collective communication patterns. In CMP applications, multicast is widely used in multithreaded programs and protocols for barrier/clock synchronization and cache coherence. Multicast routing plays an important role on the system performance of a CMP. Existing partition-based multicast routing algorithms all use static destination set partition strategy which lacks the global view of path optimization. In this paper, we propose an efficient Dynamic Partition Merging (DPM)-based multicast routing algorithm. The proposed algorithm divides the multicast destination set into partitions dynamically by comparing the routing cost of different partition merging options and selecting the merged partitions with lower cost. The simulation results of synthetic traffic and PARSEC benchmark applications confirm that the proposed algorithm outperforms the existing path-based routing algorithms. The proposed algorithm is able to improve up to 23\% in average packet latency and 14\% in power consumption against the existing multipath routing algorithm when tested in PARSEC benchmark workloads.