Communication-avoiding micro-architecture to compute Xcorr scores for peptide identification

TL;DR

This paper introduces a novel micro-architecture that reduces communication overhead in peptide spectrum matching, significantly accelerating the computation of Xcorr scores for proteomics analysis.

Contribution

It presents a communication-avoiding micro-architecture with local caching, peptide pre-fetching, and a custom broadcast bus to improve efficiency in peptide identification.

Findings

24x performance improvement over CPU implementation

Reduced DRAM accesses and improved data utilization

Efficient parallelism and synchronization in micro-architecture

Abstract

Database algorithms play a crucial part in systems biology studies by identifying proteins from mass spectrometry data. Many of these database search algorithms incur huge computational costs by computing similarity scores for each pair of sparse experimental spectrum and candidate theoretical spectrum vectors. Modern MS instrumentation techniques which are capable of generating high-resolution spectrometry data require comparison against an enormous search space, further emphasizing the need of efficient accelerators. Recent research has shown that the overall cost of scoring, and deducing peptides is dominated by the communication costs between different hierarchies of memory and processing units. However, these communication costs are seldom considered in accelerator-based architectures leading to inefficient DRAM accesses, and poor data-utilization due to irregular memory access patterns. In this paper, we propose a novel communication-avoiding micro-architecture to compute cross-correlation based similarity score by utilizing efficient local cache, and peptide pre-fetching to minimize DRAM accesses, and a custom-designed peptide broadcast bus to allow input reuse. An efficient bus arbitration scheme was designed, and implemented to minimize synchronization cost and exploit parallelism of processing elements. Our simulation results show that the proposed micro-architecture performs on average 24x better than a CPU implementation running on a 3.6 GHz Intel i7-4970 processor with 16GB memory.