A Highly Linear and Flexible FPGA-Based Time-to-Digital Converter

TL;DR

This paper introduces a novel FPGA-based TDC design that achieves high linearity and zero empty bins using a single delay line and state encoding, surpassing previous methods in performance.

Contribution

A new TDC architecture using state encoding instead of thermometer codes, eliminating the need for compensation and improving linearity in FPGA implementations.

Findings

Achieved differential non-linearity (DNL) within [-1, 1] for various time resolutions.

No empty histogram bins observed across tested resolutions.

Outperforms previous FPGA-based TDCs in linearity and simplicity.

Abstract

Time-to-Digital Converters (TDCs) are major components for the measurements of time intervals. Recent developments in Field-Programmable Gate Array (FPGA) have enabled the opportunity to implement high-performance TDCs, which were only possible using dedicated hardware. In order to eliminate empty histogram bins and achieve a higher level of linearity, FPGA-based TDCs typically apply compensation methods either using multiple delay lines consuming more resources or post-processing, leading to a permanent loss of temporal information. We propose a novel TDC with a single delay line and without compensation to realize a highly linear TDC by encoding the states of the delay lines instead of the thermometer code used in the conventional TDCs. The experimental results show our states-based approach achieves an improved Differential Non-Linearity (DNL) of [-0.998, -1.533] for time resolution of 5.00 ps, [-0.44,0.49] for 10.04 ps, [-0.16, 0.19] for 21.65 ps, [-0.10, 0.11] for 43.87 ps, [-0.06, 0.07] for 64.12 ps, and [-0.07, 0.05] for 87.73 ps, whilst no empty bins have been observed. To our knowledge, the achieved raw linearity together with the zero empty bins and a simple delay line structure exceeds previously reported of the FPGA-based TDCs.