A 51.3 TOPS/W, 134.4 GOPS In-memory Binary Image Filtering in 65nm CMOS
Sumon Kumar Bose, Deepak Singla, and Arindam Basu

TL;DR
This paper introduces an in-memory computing architecture using 6T-SRAM for energy-efficient image denoising in neuromorphic vision sensors, achieving high throughput and energy efficiency while maintaining accuracy.
Contribution
It presents a novel in-memory filtering framework with a non-overlap median filter leveraging 6T-SRAM's read disturb phenomenon, demonstrating significant energy and speed improvements.
Findings
Achieves >70x energy savings over digital implementations.
Provides >3x faster processing times.
Attains 51.3 TOPS/W energy efficiency, comparable to state-of-the-art in-memory processors.
Abstract
Neuromorphic vision sensors (NVS) can enable energy savings due to their event-driven that exploits the temporal redundancy in video streams from a stationary camera. However, noise-driven events lead to the false triggering of the object recognition processor. Image denoise operations require memoryintensive processing leading to a bottleneck in energy and latency. In this paper, we present in-memory filtering (IMF), a 6TSRAM in-memory computing based image denoising for eventbased binary image (EBBI) frame from an NVS. We propose a non-overlap median filter (NOMF) for image denoising. An inmemory computing framework enables hardware implementation of NOMF leveraging the inherent read disturb phenomenon of 6T-SRAM. To demonstrate the energy-saving and effectiveness of the algorithm, we fabricated the proposed architecture in a 65nm CMOS process. As compared to fully digital…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
