Lightweight Hardware Transform Design for the Versatile Video Coding 4K ASIC Decoders
Ibrahim Farhat, Wassim Hamidouche, Adrien Grill, Daniel M\'enard and, Olivier D\'eforges

TL;DR
This paper introduces a low-area, high-speed hardware architecture for inverse transforms in VVC decoders, enabling real-time 4K video decoding on ASICs with energy efficiency.
Contribution
It presents a multi-standard, area-efficient ASIC architecture for inverse VVC transforms supporting multiple video standards with high throughput.
Findings
Supports 600MHz operation for real-time 4K decoding at 30fps
Uses 64 multipliers in a pipelined design for efficiency
Achieves constant throughput and latency across block sizes
Abstract
Versatile Video Coding (VVC) is the next generation video coding standard finalized in July 2020. VVC introduces new coding tools enhancing the coding efficiency compared to its predecessor High Efficiency Video Coding (HEVC). These new tools have a significant impact on the VVC software decoder complexity estimated to 2 times HEVC decoder complexity. In particular, the transform module includes in VVC separable and non-separable transforms named Multiple Transform Selection (MTS) and Low Frequency Non-Separable Transform (LFNST) tools, respectively. In this paper, we present an area-efficient hardware architecture of the inverse transform module for a VVC decoder. The proposed design uses a total of 64 regular multipliers in a pipelined architecture targeting Application-Specific Integrated Circuit (ASIC) platforms. It consists in a multi-standard architecture that supports the…
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