Error Floor Analysis of LDPC Column Layered Decoders

TL;DR

This paper analyzes the error floor of LDPC column layered decoders using a linear model of trapping set dynamics, and proposes a scheduling algorithm to minimize the error floor, verified by simulations.

Contribution

It introduces a novel linear state-space model for trapping set analysis in layered LDPC decoders and develops an algorithm to optimize message scheduling for lower error floors.

Findings

The model accurately predicts the error floor behavior.

Scheduling significantly impacts the error floor levels.

Optimized schedules can reduce the error floor effectively.

Abstract

In this paper, we analyze the error floor of column layered decoders, also known as shuffled decoders, for low-density parity-check (LDPC) codes under saturating sum-product algorithm (SPA). To estimate the error floor, we evaluate the failure rate of different trapping sets (TSs) that contribute to the frame error rate in the error floor region. For each such TS, we model the dynamics of SPA in the vicinity of the TS by a linear state-space model that incorporates the information of the layered message-passing schedule. Consequently, the model parameters and the failure rate of the TS change as a result of the change in the order by which the messages of different layers are updated. This, in turn, causes the error floor of the code to change as a function of scheduling. Based on the proposed analysis, we then devise an efficient search algorithm to find a schedule that minimizes the error floor. Simulation results are presented to verify the accuracy of the proposed error floor estimation technique.