A Resolution-Adaptive 8 mm$^\text{2}$ 9.98 Gb/s 39.7 pJ/b 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS

TL;DR

This paper introduces a resolution-adaptive all-digital mmWave MU-MIMO receiver ASIC that dynamically adjusts data converter resolution to optimize power efficiency and performance in real-time scenarios.

Contribution

It presents the first resolution-adaptive all-digital receiver ASIC for mmWave MU-MIMO, integrating programmable ADCs and a spatial equalizer in 65nm CMOS.

Findings

Achieves 9.98 Gb/s throughput with 6-bit ADCs and 4-bit equalizer.

At least 2x more energy-efficient than existing designs.

Scalable 32-antenna design in 65nm CMOS.

Abstract

All-digital millimeter-wave (mmWave) massive multi-user multiple-input multiple-output (MU-MIMO) receivers enable extreme data rates but require high power consumption. In order to reduce power consumption, this paper presents the first resolution-adaptive all-digital receiver ASIC that is able to adjust the resolution of the data-converters and baseband-processing engine to the instantaneous communication scenario. The scalable 32-antenna, 65 nm CMOS receiver occupies a total area of 8 mm$^\text{2}$ and integrates analog-to-digital converters (ADCs) with programmable gain and resolution, beamspace channel estimation, and a resolution-adaptive processing-in-memory spatial equalizer. With 6-bit ADC samples and a 4-bit spatial equalizer, our ASIC achieves a throughput of 9.98 Gb/s while being at least 2x more energy-efficient than state-of-the-art designs.