A massively scalable Time-to-Digital Converter with a PLL-free calibration system in a commercial 130 nm process

TL;DR

This paper presents a highly scalable Time-to-Digital Converter in 130 nm technology, featuring a PLL-free calibration system, high linearity, and suitability for large-scale applications like physics and medical imaging.

Contribution

It introduces a novel differential 9-stage ring oscillator design with an analytical linearity model and an event-by-event self-calibration system eliminating the need for PLL synchronization.

Findings

Achieved 33.6 ps LSB resolution with high linearity (DNL ≤ 1.3 LSB, INL ≤ 2 LSB)

Demonstrated low power consumption of 5.4 mW

Validated performance through fabricated test chip

Abstract

A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along with an analytical model of linearity. The model allowed us to understand the source of the performance superiority (in terms of linearity) of our design and to predict further improvements. The oscillator is integrated in a event-by-event self-calibration system that allows avoiding any PLL-based synchronization. For this reason and for the compactness and simplicity of the architecture, the proposed TDC is suitable for applications in which a large number of converters and a massive parallelization are required such as High-Energy Physics and medical imaging detector systems. A test chip for the TDC has been fabricated and tested. The TDC shows a DNL$\leq$1.3 LSB, an INL$\leq$2 LSB and a single-shot precision of 19.5 ps (0.58 LSB). The chip dissipates a power of 5.4 mW overall.