Architecture-Specific Performance Optimization of Compute-Intensive FaaS Functions

TL;DR

This paper investigates architecture-specific optimizations for compute-intensive FaaS functions, demonstrating significant performance improvements and cost savings by tailoring code to underlying processor architectures using JIT compilation.

Contribution

It introduces a method to optimize FaaS functions for specific processor architectures, achieving notable performance gains and cost reductions on Google Cloud Functions.

Findings

Performance improved by up to 12.8x

Cost savings of approximately 73.4%

Architecture-specific tuning yields significant speedups

Abstract

FaaS allows an application to be decomposed into functions that are executed on a FaaS platform. The FaaS platform is responsible for the resource provisioning of the functions. Recently, there is a growing trend towards the execution of compute-intensive FaaS functions that run for several seconds. However, due to the billing policies followed by commercial FaaS offerings, the execution of these functions can incur significantly higher costs. Moreover, due to the abstraction of underlying processor architectures on which the functions are executed, the performance optimization of these functions is challenging. As a result, most FaaS functions use pre-compiled libraries generic to x86-64 leading to performance degradation. In this paper, we examine the underlying processor architectures for Google Cloud Functions (GCF) and determine their prevalence across the 19 available GCF regions. We modify, adapt, and optimize three compute-intensive FaaS workloads written in Python using Numba, a JIT compiler based on LLVM, and present results wrt performance, memory consumption, and costs on GCF. Results from our experiments show that the optimization of FaaS functions can improve performance by 12.8x (geometric mean) and save costs by 73.4% on average for the three functions. Our results show that optimization of the FaaS functions for the specific architecture is very important. We achieved a maximum speedup of 1.79x by tuning the function especially for the instruction set of the underlying processor architecture.