Miniaturization of Josephson junction for digital superconducting circuits

TL;DR

This paper explores the design and theoretical analysis of nanoscale Josephson junctions, particularly SN-N-NS types, for use in digital superconducting circuits, emphasizing scalability, high critical current, and reproducibility.

Contribution

It introduces the SN-N-NS Josephson junction with variable thickness bridge geometry as a promising scalable option for superconducting digital technology.

Findings

SN-N-NS junctions can achieve high I_c R_n products.

Theoretical conditions for superconductivity in the junction are derived.

Fabrication from Nb/Cu materials is feasible with existing technology.

Abstract

In this work, we briefly overview various options for Josephson junctions which should be scalable down to nanometer range for utilization in nanoscale digital superconducting technology. Such junctions should possess high values of critical current, $I_c$, and normal state resistance, $R_n$. Another requirement is the high reproducibility of the junction parameters across a wafer in a fabrication process. We argue that Superconductor - Normal metal - Superconductor (SN-N-NS) Josephson junction of "variable thickness bridge" geometry is a promising choice to meet these requirements. Theoretical analysis of SN-N-NS junction is performed in the case where the distance between the S-electrodes is comparable to the coherence length of the N-material. The restriction on the junction geometrical parameters providing the existence of superconductivity in the S-electrodes is derived for the current flowing through the junction of an order of $I_c$. The junction heating, as well as available mechanisms for the heat removal, is analyzed. The obtained results show that an SN-N-NS junction with a high (sub-millivolt) value of $I_cR_n$ product can be fabricated from a broadly utilized combination of materials like Nb/Cu using well-established technological processes. The junction area can be scaled down to that of semiconductor transistors fabricated in the frame of a 40-nm process.