A unified polar decoder platform for low-power and low-cost devices

TL;DR

This paper presents a versatile polar decoding platform optimized for low-power, low-cost devices, supporting multiple decoding algorithms within a unified, resource-efficient architecture.

Contribution

It introduces a unified architecture supporting various polar decoders, emphasizing serialization and resource sharing to minimize cost and power consumption.

Findings

Serial SCL-8 decoder is only 3 times larger than an SC decoder

Performance simulation shows reduced energy consumption

Hardware implementation confirms low-cost, low-power design

Abstract

In this paper, we design a polar decoding platform for diverse application scenarios that require low-cost and low-power communications. Specifically, prevalent polar decoders such as successive cancellation (SC), SC-list (SCL) and Fano decoders are all supported under the same architecture. Unlike high-throughput or low-latency decoders that promote parallelism, this architecture promotes serialization by repeatedly calling a ``sub-process'' that is executed by a core module. The resulting serial SCL-8 decoder is only 3 times as big as an SC decoder. Cost and power are minimized through resource sharing and adaptive decoding techniques, etc. We carried out performance simulation and hardware implementation to evaluate the actual chip area and energy consumption.