Fast polar codes for terabits-per-second throughput communications

TL;DR

This paper introduces fast polar codes and a highly parallel SC decoding architecture to achieve terabit-per-second throughput with high energy and area efficiency in ASIC implementations.

Contribution

It proposes a novel code construction called fast polar codes, optimized jointly with a parallel decoding architecture for ultra-high throughput communications.

Findings

Achieved 4 Tbps/mm^2 area efficiency with unrolled decoder.

Reduced energy per bit to 0.63 pJ/bit with unrolled decoder.

Improved area efficiency by 2.66 times and saved 33% energy over previous methods.

Abstract

Targeting high-throughput and low-power communications, we implement two successive cancellation (SC) decoders for polar codes. With $16nm$ ASIC technology, the area efficiency and energy efficiency are $4Tbps/mm^2$ and $0.63pJ/bit$, respectively, for the unrolled decoder, and $561Gbps/mm^2$ and $1.21pJ/bit$, respectively, for the recursive decoder. To achieve such a high throughput, a novel code construction, coined as fast polar codes, is proposed and jointly optimized with a highly-parallel SC decoding architecture. First, we reuse existing modules to fast decode more outer code blocks, and then modify code construction to facilitate faster decoding for all outer code blocks up to a degree of parallelism of $16$. Furthermore, parallel comparison circuits and bit quantization schemes are customized for hardware implementation. Collectively, they contribute to an $2.66\times$ area efficiency improvement and $33\%$ energy saving over the state of the art.