TCAD Modeling of Cryogenic nMOSFET ON-State Current and Subthreshold Slope

TL;DR

This study demonstrates that a single TCAD model can accurately simulate the ON current and subthreshold slope of a 0.35um nMOSFET at both room and cryogenic temperatures, highlighting the role of interface traps.

Contribution

It introduces a unified modeling approach using interface traps to replicate cryogenic and room temperature device behaviors, aiding in device optimization.

Findings

Model accurately predicts ON current and SS at 300K and 5K.

Interface traps with density <2e12cm-2 can explain abnormal SS.

Cryogenic temperature reduces DIBL, affecting device design.

Abstract

In this paper, through careful calibration, we demonstrate the possibility of using a single set of models and parameters to model the ON current and Sub-threshold Slope (SS) of an nMOSFET at 300K and 5K using Technology Computer-Aided Design (TCAD). The device used is a 0.35um technology nMOSFET with W/L=10um/10um. We show that it is possible to model the abnormal SS by using interface acceptor traps with a density less than 2e12cm-2. We also propose trap distribution profiles in the energy space that can be used to reproduce other observed SS from 4K to 300K. Although this work does not prove or disprove any possible origin of the abnormal SS, it shows that one cannot completely rule out the interfacial traps as the origin and it shows that interfacial traps can be used to model the abnormal SS before the origin is fully understood. We also show that Drain-Induced-Barrier-Lowering (DIBL) is much reduced at cryogenic temperature due to the abnormal slope and the device optimization strategy might need to be revised.