Efficient Topology Optimized Couplers for On-Chip Single-photon Sources

TL;DR

This paper introduces an adjoint topology optimization method to design high-efficiency couplers for on-chip single-photon sources, significantly improving coupling efficiency and addressing fabrication and placement uncertainties.

Contribution

The work presents a novel optimization scheme for designing efficient SPS-to-waveguide couplers, accounting for fabrication constraints and SPS position variability.

Findings

Achieved an average coupling efficiency of 78%

Developed a library of designs for various SPS positions

Gained physics-based insights into device geometry-performance relationships

Abstract

Room temperature single-photon sources (SPSs) are critical for the emerging practical quantum applications such as on-chip photonic circuity for quantum communications systems and integrated quantum sensors. However, direct integration of an SPS into on-chip photonic systems remains challenging due to low coupling efficiencies between the SPS and the photonic circuitry that often involve size mismatch and dissimilar materials. Here, we develop an adjoint topology optimization scheme to design high-efficiency couplers between a photonic waveguide and SPS in hexagonal boron nitride (hBN). The algorithm accounts for fabrication constraints and the SPS location uncertainty. First, a library of designs for the different positions of the hBN flake containing an SPS with respect to a Si$_{3}$N$_{4}$ waveguide is generated, demonstrating an average coupling efficiency of 78%. Then, the designs are inspected with dimensionality reduction technique to investigate the relationship between the device geometry (topology) and performance. The fundamental, physics-based intuition gained from this approach could enable the design of high-performance quantum devices