Scaled-Time-Attention Robust Edge Network

TL;DR

The paper introduces STARE, a new neural network architecture based on delay-loop reservoir concepts, optimized for edge applications with improved efficiency, simplicity, and performance in temporal feature extraction and classification.

Contribution

It presents the novel STARE architecture that combines hyperdimensional space and non-multiply-and-add computation, suitable for edge devices and temporal data processing.

Findings

Effective in drone vs bird detection using dual-loop configuration

Achieves performance close to state-of-the-art deep neural networks in RF modulation classification

Outperforms LSTM in Mackey Glass time series prediction

Abstract

This paper describes a systematic approach towards building a new family of neural networks based on a delay-loop version of a reservoir neural network. The resulting architecture, called Scaled-Time-Attention Robust Edge (STARE) network, exploits hyper dimensional space and non-multiply-and-add computation to achieve a simpler architecture, which has shallow layers, is simple to train, and is better suited for Edge applications, such as Internet of Things (IoT), over traditional deep neural networks. STARE incorporates new AI concepts such as Attention and Context, and is best suited for temporal feature extraction and classification. We demonstrate that STARE is applicable to a variety of applications with improved performance and lower implementation complexity. In particular, we showed a novel way of applying a dual-loop configuration to detection and identification of drone vs bird in a counter Unmanned Air Systems (UAS) detection application by exploiting both spatial (video frame) and temporal (trajectory) information. We also demonstrated that the STARE performance approaches that of a State-of-the-Art deep neural network in classifying RF modulations, and outperforms Long Short-term Memory (LSTM) in a special case of Mackey Glass time series prediction. To demonstrate hardware efficiency, we designed and developed an FPGA implementation of the STARE algorithm to demonstrate its low-power and high-throughput operations. In addition, we illustrate an efficient structure for integrating a massively parallel implementation of the STARE algorithm for ASIC implementation.