Vertical GaN Devices: Process and Reliability

TL;DR

This paper reviews advancements and challenges in process and reliability for vertical GaN devices, highlighting 200 mm CMOS-compatible technology, substrate innovations, and epitaxy methods to improve device performance and robustness.

Contribution

It introduces a 200 mm CTE matched substrate approach and coalescence epitaxy for GaN-on-Silicon, advancing vertical GaN device fabrication and reliability.

Findings

Successful demonstration of 200 mm CTE matched substrates for vertical transistors

Gate module optimizations improve device robustness

Coalescence epitaxy enables low-dislocation thick GaN layers

Abstract

This paper reviews recent progress and key challenges in process and reliability for high-performance vertical GaN transistors and diodes, focusing on the 200 mm CMOS-compatible technology. We particularly demonstrated the potential of using 200 mm diameter CTE matched substrates for vertical power transistors, and gate module optimizations for device robustness. An alternative technology path based on coalescence epitaxy of GaN-on-Silicon is also introduced, which could enable thick drift layers of very low dislocation density.