Experimental Extraction and Simulation of Charge Trapping during Endurance of FeFET with TiN/HfZrO/SiO2/Si (MFIS) Gate Structure

TL;DR

This study experimentally extracts and models charge trapping in FeFET devices during endurance fatigue, revealing increased trapped charges correlate with memory window reduction without degrading ferroelectric properties.

Contribution

First direct experimental measurement of trapped charges during FeFET endurance fatigue and modeling of their impact on device performance.

Findings

Trapped charges increase during endurance fatigue.

Memory window decreases due to trapped electrons, not ferroelectric degradation.

Trap density in the upper bandgap rises with fatigue.

Abstract

We investigate the charge trapping during endurance fatigue of FeFET with TiN/Hf0.5Zr0.5O2/SiO2/Si (MFIS) gate structure. We propose a method of experimentally extracting the number of trapped charges during the memory operation, by measuring the charges in the metal gate and Si substrate. We verify that the amount of trapped charges increases during the endurance fatigue process. This is the first time that the trapped charges are directly experimentally extracted and verified to increase during endurance fatigue. Moreover, we model the interplay between the trapped charges and ferroelectric polarization switching during endurance fatigue. Through the consistency of experimental results and simulated data, we demonstrate that as the memory window decreases: 1) The ferroelectric characteristic of Hf0.5Zr0.5O2 is not degraded. 2) The trap density in the upper bandgap of the gate stacks increases. 3) The reason for memory window decrease is increased trapped electrons after program operation but not related to hole trapping/de-trapping. Our work is helpful to study the charge trapping behavior of FeFET and the related endurance fatigue process.