Fully CMOS-compatible passive TiO2-based memristor crossbars for in-memory computing

TL;DR

This paper presents a CMOS-compatible fabrication process for TiO2-based memristor crossbars that enable in-memory computing with multilevel synaptic-like switching, suitable for neuromorphic hardware.

Contribution

It introduces a fully CMOS-compatible process for TiO2 memristor crossbars with optimized electrodes and demonstrates multilevel conductance programming for neuromorphic applications.

Findings

Successful fabrication of TiO2 memristor crossbars with low surface roughness.

Demonstration of multilevel conductance with at least 3 bits capacity.

Analysis of variability and reproducibility in memristor switching.

Abstract

Brain-inspired computing and neuromorphic hardware are promising approaches that offer great potential to overcome limitations faced by current computing paradigms based on traditional von-Neumann architecture. In this regard, interest in developing memristor crossbar arrays has increased due to their ability to natively perform in-memory computing and fundamental synaptic operations required for neural network implementation. For optimal efficiency, crossbar-based circuits need to be compatible with fabrication processes and materials of industrial CMOS technologies. Herein, we report a complete CMOS-compatible fabrication process of TiO2-based passive memristor crossbars with 700 nm wide electrodes. We show successful bottom electrode fabrication by a damascene process, resulting in an optimised topography and a surface roughness as low as 1.1 nm. DC sweeps and voltage pulse programming yield statistical results related to synaptic-like multilevel switching. Both cycle-to-cycle and device-to-device variability are investigated. Analogue programming of the conductance using sequences of 200 ns voltage pulses suggest that the fabricated memories have a multilevel capacity of at least 3 bits due to the cycle-to-cycle reproducibility.